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19-1537; Rev 4; 3/09
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
General Description
The MAX3676 is a complete clock-recovery and dataretiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications. The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-ofpower (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL). Single +3.3V or +5.0V Power Supply Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications Low Power: 237mW at +3.3V Selectable Data Inputs, Differential PECL or Analog Received-Signal-Strength Indicator Loss-of-Power and Loss-of-Lock Monitors Differential PECL Clock and Data Outputs No External Reference Clock Required
Features
MAX3676
Ordering Information
PART MAX3676EHJ MAX3676EHJ+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP 32 TQFP
Applications
SDH/SONET Receivers and Regenerators SDH/SONET Access Nodes Add/Drop Multiplexers ATM Switches Digital Cross-Connects
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
+3.3V +3.3V 0.1F INSEL VCC CIN 0.01F ZO = 50 100 IN OUTGND COMP 220pF CFILT OLC+ OLC- GND CFILT 47nF COLC 33nF R2 R1 20k RSSI INV VTH LOP ZO = 50 82 82 ZO = 50 C +3.3V IN 0.01F VCC ADISCLKO+ 130 SCLKOZO = 50 130 ADI+ DDI+ DDISDO100pF PHOTODIODE 82 82 PHADJ+ PHADJFIL+ FILLOL SDO+ ZO = 50 ZO = 50 CF 2.2F CLOL 0.01F 130 0.01F +3.3V
130
FILT
MAX3664
INREF OUT+
MAX3676
+3.3V
________________________________________________________________ Maxim Integrated Products
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +6.5V Input Voltage Levels, DDI+, DDI-, ADI+, ADI- ...........................-0.5V to (VCC + 0.5V) Input Differential Voltage (ADI+) - (ADI-)...............................3V PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mA LOL, LOP, INSEL, PHADJ+, PHADJ- .........-0.5V to (VCC + 0.5V) FIL-, OLC+, OLC-, RSSI, VTH ....................-0.5V to (VCC + 0.5V) (OLC+) - (OLC-).....................................................................3V FIL+..................................................Internally connected to VCC CFILT ...............................................(VCC - 2.5V) to (VCC + 0.5V) INV.........................................................................-0.5V to +2.0V Continuous Power Dissipation (TA = +85C) TQFP (derate 18.7mW/C above +85C) ................1214.8mW Operating Junction Temperature Range ...........-40C to +150C Storage Temperature Range .............................-65C to +150C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Supply Current PECL Input-Voltage High PECL Input-Voltage Low PECL Input-Current High PECL Input-Current Low PECL Output-Voltage High PECL Output-Voltage Low LOP, LOL Voltage High LOP, LOL Voltage Low INV Input Bias Voltage SYMBOL ICC VIH VIL IIH IIL VOH VOL VOH VOL 4k between INV and VTH 1.10 1.23 TA = 0C to +85C TA = -40C TA = 0C to +85C TA = -40C CONDITIONS MAX3676EHJ, PECL outputs unterminated INSEL = VCC INSEL = GND VCC - 1.16 VCC - 1.81 -10 -10 VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC - 1.83 2.4 0.4 1.30 MIN TYP 72 51 MAX 111 mA 81 VCC - 0.88 VCC - 1.48 10 10 VCC - 0.88 VCC - 0.88 VCC - 1.620 VCC - 1.555 V V A A V V V V V UNITS
Note 1: At TA = -40C, DC characteristics are guaranteed by design and characterization.
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Notes 2, 3) PARAMETER Differential Input Voltage Range Input-Referred Noise Power-Detect Hysteresis Limiting Amplifier SmallSignal Bandwidth RSSI Output Voltage Threshold Voltage LOP Threshold Accuracy RSSI Linearity RSSI Slope Loop Bandwidth Jitter Generation (Note 9) Jitter-Transfer Peaking VTH BW SYMBOL VID VN CONDITIONS BER < 10-10, ADI inputs (Note 4) ADI inputs (Notes 5, 6) (Note 7) (ADI+) - (ADI-) = 2mVP-P (ADI+) - (ADI-) = 20mVP-P (Note 6) (Note 6) (ADI+) - (ADI-) = 2mVP-P to 50mVP-P (ADI+) - (ADI-) = 2mVP-P to 50mVP-P (Note 8) CF = 2.2F CF = 2.2F CF = 2.2F f = 10kHz Jitter Tolerance (Note 10) CF = 2.2F f = 25kHz f = 250kHz f = 1MHz Maximum Consecutive Input Run Length (1 or 0) Clock Transition Time Data Transition Time Serial Clock-to-Q Delay Serial Clock Frequency tr, tf tr, tf tCLK-Q fSCLK 20% to 80% 20% to 80% 140 (Note 11) 0.55 0.45 -2 0.7 26 250 2.0 0.03 8.9 3.64 0.77 0.69 1200 205 180 275 622.08 245 230 400 Bits ps ps ps MHz UI 500 2.6 0.08 3 650 1.40 1.93 1.41 +2 MIN 0.003 80 6 TYP MAX 1.2000 UNITS VP-P VRMS dB MHz V V dB % mV/dB kHz mUI dB
MAX3676
Note 2: AC parameters are guaranteed by design and characterization. Note 3: The MAX3676 is characterized with a PRBS of 223 - 1 maintaining a BER of 10-10 having a confidence level of 99.9%. Note 4: A lower minimum input voltage of 2mVP-P is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVP-P. Note 5: Hysteresis = 20log(VRELEASE/VASSERT). Note 6: R1 = 20k, R2 = 3.0k, resulting in VRELEASE 3.6mVP-P. Note 7: Small-signal bandwidth cannot be measured directly. Note 8: RSSI slope = [VRSSI2 - VRSSI1]/[20log (VID2/VID1)]. Note 9: 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns. Note 10: At jitter frequencies <10kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency jitter tolerance outperforms the instrument's measurement capability. Note 11: See Typical Operating Characteristics for worst-case distribution.
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (SINGLE-ENDED)
MAX3676 toc01
RECOVERED CLOCK JITTER
223 -1 PATTERN DATA BIT-ERROR RATE
MAX3676 toc02
BIT-ERROR RATE vs. ADI INPUT VOLTAGE
10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 400 500 600 700 800 900 1m 1.1m 1.2m INPUT VOLTAGE (V) 223 -1 PATTERN
MAX3676 toc03
10-2
223 -1 PATTERN
CLOCK WIDEBAND RMS JITTER = 5.84ps 400ps/div 20ps/div
JITTER TOLERANCE
MAX3676 toc04
JITTER TRANSFER
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 2k
MAX3676 toc05
DISTRIBUTION OF JITTER TOLERANCE (WORST-CASE CONDITIONS)
MEAN = 2.42UI = 0.227UI fJITTER = 25kHz VCC = +3.0V TA = +85C
MAX3676 toc06
10 223 -1 PATTERN
30 25 PERCENT OF UNITS (%) 20 15 10 5 0
1
JITTER TRANSFER (dB)
BELLCORE MASK
INPUT JITTER (UIP-P)
BELLCORE MASK 0.1 10k 100k 1M 10M JITTER FREQUENCY (Hz)
223 - 1 PRBS
10k
100k
700k
1.5
2.0 2.2 2.4 2.6 2.8 3.0 JITTER TOLERANCE (UIP-P)
3.5
JITTER FREQUENCY (Hz)
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
LOSS-OF-POWER ASSERT AND RELEASE LEVEL vs. DETECTOR THRESHOLD VOLTAGE
223 -1 PATTERN ANALOG VOLTAGE (mVp-p)
MAX3676 toc09
MAX3676
LOSS-OF-POWER HYSTERESIS vs. TEMPERATURE
223 -1 PATTERN VCC = +3.3V OR +5.0V
MAS3676 toc07
RECEIVED-SIGNAL-STRENGTH INDICATOR vs. INPUT VOLTAGE
2.5 2.3 223 -1 PATTERN
MAX3676 toc08
5.0 4.5 HYSTERESIS (dB) 4.0
2.7
100
LOP RELEASE 10 LOP ASSERT
RSSI (V)
2.1 1.9 1.7 1.5 1010 PATTERN
3.5 3.0 2.5 2.0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (C)
1.3 1.1 0.1 1.0 10 100 1000 INPUT VOLTAGE (mVP-P) 1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 DETECTOR THRESHOLD VOLTAGE, VTH (V)
RECEIVED-SIGNAL-STRENGTH INDICATOR vs. INPUT VOLTAGE
MAX3676 toc10
SUPPLY CURRENT vs. TEMPERATURE
MAX3676 toc11
2.7 2.5 2.3 RSSI (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.1 1.0 10 100 223 -1 PATTERN VCC = +3.3V OR +5.0V
100 90 SUPPLY CURRENT (mA) 80 70 60 50 40 30 -40 -20 0 20 40 60 80 VCC = +3.3V VCC = +5.0V
1000
100
INPUT VOLTAGE (mVP-P)
TEMPERATURE (C)
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
Pin Description
PIN 1 2 3 4, 8, 16, 24, 25 5 6 7 9, 12, 15, 18, 21, 31 10 11 13 14 17 19 20 22 23 26 27 28 29 30 32 NAME OLC+ OLCRSSI GND INV VTH LOP VCC SCLKOSCLKO+ SDOSDO+ LOL PHADJPHADJ+ FILFIL+ DDI+ DDIINSEL ADIADI+ CFILT FUNCTION Positive Offset-Correction Loop Capacitor Input Negative Offset-Correction Loop Capacitor Input Received-Signal-Strength Indicator Output Supply Ground Op Amp Inverting Input. Attach to ground if op amp is not used. Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCC if LOP function is not used. Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal is below threshold set by VTH. Positive Supply Voltage Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-. Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+. Negative Serial-Data Output, PECL, 622.08Mbps Positive Serial-Data Output, PECL, 622.08Mbps Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see the Design Procedure section). Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. Negative Filter Input. PLL loop filter connection. Connect a 2.2F capacitor between FIL- and FIL+. Positive Filter Input. PLL loop filter connection. Internally connected to VCC. Positive Digital Data Input, PECL, 622.08Mbps serial-data stream Negative Digital Data Input, PECL, 622.08Mbps serial-data stream Input Select. Connect to GND to select digital data inputs or VCC for analog data inputs. Negative Analog Data Input, 622.08Mbps serial-data stream Positive Analog Data Input, 622.08Mbps serial-data stream RSSI Filter Capacitor Input. Connect a 47nF capacitor between CFILT and VCC.
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
LOL VCC 6k SDO+ D Q SDOPECL PHADJ+ PHADJFIL+ FIL-
DDI+ DDIPECL INSEL PHASE/FREQ DETECTOR
I
SCLKO+ PECL SCLKO-
FILTER
VCO Q 622.08MHz
VCC ADIADI+ LIMITER 42dB BIAS 1.23V 6k
POWER DETECT OFFSET CORRECTION
MAX3676
OLC+
OLC-
CFILT
RSSI
INV
VTH
LOP
Figure 1. Functional Diagram
_______________Detailed Description
The block diagram in Figure 1 shows the MAX3676's architecture. It consists of a limiting-amplifier input stage followed by a fully integrated clock/data-recovery (CDR) block implemented with a PLL. The input stage is selectable between a limiting amplifier or a simple PECL input buffer. The limiting amplifier provides an LOP monitor and an RSSI output. The PLL consists of a phase/frequency detector (PFD), a loop filter amplifier, and a voltage-controlled oscillator (VCO).
Limiting Amplifier
The MAX3676's on-chip limiting amplifier accepts an input signal level from 3.0mVP-P to 1.2VP-P. The amplifier consists of a cascade of gain stages that include fullwave logarithmic detectors. The combined small-signal gain is approximately 42dB, and the -3dB bandwidth is 650MHz. Input-referred noise is typically 80VRMS, pro-
viding excellent sensitivity for small-amplitude data streams. In addition to driving the CDR, the limiting amplifier provides both an RSSI output and an LOP monitor that allow the user to program the threshold voltage. The RSSI circuitry provides an output voltage that is linearly proportional to the input power (in decibels) detected between the ADI+ and ADI- input pins and is sensitive enough to reliably detect signals as small as 2mVP-P (see the Typical Operating Characteristics). Input DC offset reduces the accuracy of the power detector; therefore, an integrated feedback loop is included that automatically nulls the input offset of the gain stage. The addition of this offset-correction loop requires that the input signal be AC-coupled when using the ADI+ and ADI- inputs. Finally, for applications that do not require the limiting amplifier, selecting the digital inputs conserves power by turning off the postamplifier block.
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
Phase Detector
The phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the incoming data. The external phase adjustment pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. into the MAX3676 to remove the input offset. DC-coupling to the ADI+ and ADI- inputs is not allowed, as this would prevent the proper functioning of the DC offsetcorrection circuitry. The differential input impedance (ZIN) is approximately 2.5k. The impedance between OLC+ and OLC- (ZOLC) is approximately 120k. Take care when setting the combined low-frequency cutoff (fCUTOFF), due to the input DC-blocking capacitor (CIN) and the offset correction loop capacitor (COLC). See Table 1 for selecting the values of CIN and COLC. These values ensure that the poles associated with CIN and COLC work together to provide a flat response at the lower -3dB corner frequency (no gain peaking). CIN must be a low-TC, high-quality capacitor of type X7R or better in order to minimize fCUTOFF deviations. COLC must be a capacitor of type Z5U or better.
Frequency Detector
The frequency detector incorporated into the PLL uses the input data stream edges to sample the quadrature components of the VCO clock. This generates a difference frequency that aids acquisition during startup. Depending on the polarity of the difference frequency, the PFD drives the VCO so that the difference frequency is reduced to zero. Once frequency acquisition is obtained, the frequency detector returns to a neutral state.
Loop Filter and VCO
The VCO is fully integrated, while the loop filter requires an external capacitor (CF). This filter network determines the bandwidth and peaking of the second-order PLL.
Loss-of-Power Monitor
An LOP monitor with a user-programmable threshold and a hysteresis comparator is also included with the limiting amplifier circuitry. Internally, one comparator input is tied to the RSSI output signal, and the other is tied to the threshold voltage (VTH), which is set externally and provides a trip point for the LOP indication. A low-voltage, low-drift op amp, referenced to an internal bandgap voltage (1.23V), is supplied for programming a supply independent threshold voltage. This op amp requires two external resistors to program the LOP trip point. VTH is programmable from 1.23V to 2.6V using the equation: VTH = 1.23(1 + R2/R1) The op amp can source only 100A of current. Therefore, an R1 value of 20k is recommended for proper operation. The input bias current of the op amp at the INV pin is less than 100nA.
__________________Design Procedure
Received-Signal-Strength Indicator
The RSSI output voltage is insensitive to temperature and supply fluctuations. The power detector functions as a broadband power meter that detects the total RMS power of all signals within the detector bandwidth (including input signal noise). The RSSI voltage varies linearly (in decibels) for inputs of 2mVP-P to 50mVP-P. The slope over this input range is approximately 26mV/dB. The high-speed RSSI signal is filtered to an RMS level with one external capacitor tied from CFILT to VCC. The impedance looking into CFILT is about 500 to VCC. As a result, the lower -3dB cutoff frequency is set by the following simple relationship: fFILT = 1/[2(500)CFILT] For 622Mbps applications, Maxim recommends a cutoff frequency of 6.8kHz, which requires CFILT = 47nF. The RSSI output is designed to drive a minimum load resistance of 100k to ground and a maximum of 20pF. Loads greater than 20pF must be buffered by a series resistance of 100k (i.e., voltmeter).
Table 1. Setting the Low-Frequency Cutoff
CIN 0.022F 0.010F 6800pF 4700pF 2200pF 1000pF 470pF 330pF 220pF COLC 0.15F 0.1F 0.082F 0.033F 0.015F 0.01F 3300pF 2200pF 1500pF COMBINED LOW fCUTOFF (kHz) 3.0 6.8 10 13.5 29 68 135 190 290
Input Offset Correction
The on-chip limiting amplifier provides more than 42dB of gain. A low-frequency feedback loop is integrated
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
The comparator is configured with an active-high LOP output. An on-chip, 6k pull-up resistor is provided to reduce the external part count.
MAX3676
Setting the Loop Filter
The MAX3676 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 250kHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 2 and 3 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fZ = 1 2(90) CF
OPEN-LOOP GAIN
CF = 0.22F fZ = 8.04kHz CF = 2.2F fZ = 804Hz
f (Hz) 100 1k 10k 100k 1M 10M
For an overdamped system (fZ/fL) <0.25, the jitter peaking (MP) of a second-order system can be approximated by: f MP = 20log1+ Z fL For example, using CF = 0.22F results in a jitter peaking of 0.27dB. Reducing CF below 0.22F may result in PLL instability. The recommended value for CF is 2.2F to guarantee a maximum jitter peaking of less than 0.1dB. The MAX3676 is optimally designed to acquire lock and to provide a bit-error rate (BER) of less than 10 -10 for long strings of consecutive zeros and ones. Measured results show that the MAX3676 can tolerate 1200 consecutive ones or zeros. Decreasing CF reduces the number of tolerated consecutive identical zeros and ones. CF must be a low-TC, high-quality capacitor of type X7R or better.
Figure 2. Open-Loop Transfer Function
H(J2f) (dB) CF = 0.22F 0 CLOSED-LOOP GAIN -3 CF = 2.2F
Lock Detect
The MAX3676's LOL monitor indicates when the PLL is locked. Under normal operation, the loop is locked and the LOL output signal is high. When the MAX3676 loses lock, a fast negative-edge transition occurs on LOL. The output level remains at a low level (held by CLOL) until the loop reacquires lock (Figure 4).
f (kHz) 100 1k 10k 100k 1M 10M
Figure 3. Closed-Loop Transfer Function
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3676. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. See the Loss-of-Power Monitor section for this type of indicator. quency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough.
Input and Output Terminations
The MAX3676 digital data and clock I/Os (DDI+, DDI-, SDO+, SDO-, SCLK+, and SCLK-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50 to VCC - 2V should be used with fixed-impedance transmission lines for proper termination. Make sure that the differential outputs have balanced loads. The digital data input signals (DDI+ and DDI-) are differential inputs to an emitter-coupled pair. As a result, the MAX3676 can accept differential input signals as low as 250mV. These inputs can also be driven singleended by externally biasing DDI- to the center of the voltage swing. The MAX3676's performance can be greatly affected by circuit board layout and design. Use good high-fre-
Applications Information
Driving the Limiting Amplifier Single-Ended
There are three important requirements for driving the limiting amplifier from a single-ended source (Figure 5): 1) There must be no DC-coupling to the ADI+ and ADIinputs. DC levels at these inputs disrupt the offsetcorrection loop. 2) The terminating resistor RT (50) must be referenced to the ADI- input to minimize common-mode coupling problems. 3) The low-frequency cutoff for the limiting amplifier is determined by either C IN and the 2.5k input impedance or Cb/2 together with RT. With Cb = 0.22F and RT = 50, the low-frequency cutoff is 29kHz.
LOP
OUTPUT LEVEL
Cb 0.22F
CIN 5.6nF
MAX3676 ADI+
LOL
RT 50 ADICb 0.22F
2.5k
NO DATA
ACQUIRE
LOCKED
TIME
Figure 4. Loss-of-Lock Output
Figure 5. Single-Ended Input Termination
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Reduced Power Consumption Without the Limiting Amplifier
The limiting amplifier is biased independently from the clock recovery circuitry. Grounding INSEL turns off the limiting amplifier and selects the PECL DDI inputs. In an optical receiver, the decibel change at the MAX3676 always equals 2x the optical decibel change. The MAX3676's typical voltage hysteresis is 3.0dB. This provides an optical hysteresis of 1.5dB.
MAX3676
Converting Average Optical Power to Signal Amplitude
Many of the MAX3676's specifications relate to inputsignal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 2 and Figure 6 are helpful for converting optical power to input signal when designing with the MAX3676. In an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in Table 2 by the photodiode responsivity and transimpedance amplifier gain.
Jitter in Optical Receivers
Timing jitter, edge speeds, aberrations, optical dispersion, and attenuation all impact the performance of high-speed clock recovery for SDH/SONET receivers (Figure 7). These effects decrease the time available for error-free data recovery by reducing the received "eye opening" of nonreturn-to-zero (NRZ) transmitted signals.
P1
Optical Hysteresis
Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (power). At the inputs to the MAX3676 limiting amplifier, the power is VIN2/R. If a receiver's optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage at the input to the MAX3676 also increases by a factor of two. The optical power increase is: 10log(2x/x) = 10log(2) = +3dB At the MAX3676, the voltage increase is: 10 log
PAVE
P0 TIME
Figure 6. Optical Power Relations
( 2VIN ) 2/ R
VIN 2/ R
= 10 log(2 2 ) = 20 log(2) = +6dB
AMPLITUDE
Table 2. Optical-Power Relations*
PARAMETER Average Power Extinction Ratio Optical Power of a "1" Optical Power of a "0" Signal Amplitude SYMBOL PAVG re P1 P0 RELATION
MIDPOINT
PAVG = P0 + P1 / 2 re = P1 / P0 P1 = 2PAVG
AMPLITUDE
(
)
EYE DIAGRAM WITH NO TIMING JITTER
TIME
re re + 1
MIDPOINT
P0 = 2PAVG / re + 1
()
(re - 1)
re + 1
PIN
PIN = P1 - P0 = 2PAVG
EFFECTS OF TIMING JITTER ON EYE DIAGRAM
TIME
*Assuming a 50% average input-data duty cycle.
Figure 7. Eye Diagram With and Without Timing Jitter
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622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Optical receivers, incorporating transimpedance preamplifiers and limiting postamplifiers, can significantly clean up the effects of dispersion and attenuation. In addition, these amplifiers can provide fast transitions with minimal aberrations to the subsequent CDR blocks. However, these stages also add distortions to the midpoint crossing, contributing to timing jitter. Timing jitter is one of the most critical technical issues to consider when developing optical receivers and CDR circuits. A better understanding of the different sources of jitter helps in the design and application of optical receiver modules and integrated CDR solutions. SDH/SONET specifications are well defined regarding the amount of jitter tolerance allowed at the inputs of optical receivers, as well as jitter peaking requirements, but they do little to define the different sources of jitter. The jitter that must be tolerated at an optical receiver input involves three significant sources, all of which are present in varying degrees in typical receiver systems: 1) Random jitter (RJ) 2) Pattern-dependent jitter (PDJ) 3) Pulse-width distortion (PWD)
MAX3676
of the transitions, the lower the effect of noise on random jitter. The following equation is a simple worstcase estimation of random jitter: RJ (rms) = (rms noise)/(slew rate)
Pattern-Dependent Jitter PDJ results from wide variations in the number of consecutive bits contained in NRZ data streams working against the bandwidth requirements of the receiver (Figure 9). The location of the lower -3dB cutoff frequency is important, and must be set to pass the low frequencies associated with long consecutive bit streams. AC-coupling is common in optical receiver design. When using a preamplifier with a highpass frequency response, select the input AC-coupling capacitor, CIN, to provide a low-frequency cutoff (fC) one decade lower than the preamplifier low-frequency cutoff. As a result, the PDJ is dominated by the low-frequency cutoff of the preamplifier.
When using a preamplifier without a highpass response with the MAX3676, the following equation provides a good starting point for choosing CIN: CIN
Random Jitter RJ is caused by random noise present during edge transitions (Figure 8). This random noise results in random midpoint crossings. All electrical systems generate some random noise; however, the faster the speed
(
-tL PDJ BW 1.25k In 1 - 0.5
)
(
)( )

where tL = duration of the longest run of consecutive bits of the same value (seconds); PDJ = maximum
DESIRED MIDPOINT CROSSING LF DROOP MIDPOINT ACTUAL MIDPOINT CROSSING 0-1 TRANSITION WITH RANDOM NOISE RANDOM JITTER MIDPOINT AMPLITUDE LONG CONSECUTIVE BIT STREAM AMPLITUDE MIDPOINT 0-1-0 BIT STREAM
LF PDJ TIME
TIME
Figure 8. Random Jitter on Edge Transition
12
Figure 9. Pattern-Dependent Jitter Due to Low-Frequency Cutoff
______________________________________________________________________________________
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
allowable pattern-dependent jitter, peak-to-peak (seconds); and BW = typical system bandwidth, normally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is still larger than desired, continue increasing the value of C IN . Note that to maintain stability when using the MAX3676 analog inputs (ADI+, ADI-), it is important to keep the low-frequency cutoff associated with COLC below the corner frequency associated with CIN (fC) (Table 1). PDJ can also be present due to insufficient high-frequency bandwidth (Figure 10). If the amplifiers are not fast enough to allow for complete transitions during single-bit patterns, or if the amplifier does not allow adequate settling time, high-frequency PDJ can result. same level (Figure 11). DC offsets and nonsymmetrical rising and falling edge speeds both contribute to PWD. For a 1-0 bit stream, calculate PWD as follows: PWD = [(width of wider pulse) (width of narrower pulse)]/2
MAX3676
Phase Adjust
The internal clock and data alignment in the MAX3676 is well maintained close to the center of the data eye. Although not required, this sampling point can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input signals to approximately 1V. A simple resistor divider with a bypass capacitor is sufficient to set up these levels. When the PHADJ inputs are not used, they should be tied directly to VCC.
Pulse-Width Distortion
Finally, PWD occurs when the midpoint crossing of a 0-1 transition and a 1-0 transition does not occur at the
0-1-0 BIT STREAM AMPLITUDE MIDPOINT
AMPLITUDE
LONG CONSECUTIVE BIT STREAM
PWD RESULTS WHEN THE WIDTH OF A ZERO DOES NOT EQUAL THE WIDTH OF A ONE. MIDPOINT tFALL tRISE
WIDTH OF A ZERO HF PDJ TIME WIDTH OF A ONE TIME
Figure 10. Pattern-Dependent Jitter Due to High-Frequency Rolloff
Figure 11. Pulse-Width Distortion
______________________________________________________________________________________
13
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3676
___________________Pin Configuration
TRANSISTOR COUNT: 2528
20 PHADJ+ 19 PHADJ-
Chip Information Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
TOP VIEW
24 GND 23 FIL+ 22 FIL21 VCC
17 LOL
18 VCC
GND DDI+ DDI-
25 26 27
16 GND 15 VCC 14 SDO+
PACKAGE TYPE 32 TQFP
PACKAGE CODE H32-4F
DOCUMENT NO. 21-0110
INSEL 28 ADI- 29 ADI+ 30
MAX3676
13 SDO12 VCC 11 SCLKO+ 10 SCLKO9 VCC
VCC 31 CFILT 32
1
2
3
4
5
6
7 LOP
OLC+
OLC-
RSSI
TQFP (5mm x 5mm) PLCC
14
______________________________________________________________________________________
GND
GND
INV
VTH
8
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 2/00 4/00 12/01 Initial release. Corrected the Package Information section. Corrected the Chip Topography. Added lead-free package to the Ordering Information table. 3 4/05 Changed the Absolute Maximum Ratings specification for Continuous Power Dissipation. Removed the dice package information from the Ordering Information and DC Electrical Characteristics tables. Added CF to the 22F capacitor and changed CF to CFILT for the 47nF capacitor in the Typical Operating Circuit and corrected the capacitor references in the Loop Filter and VCO and Received-Signal-Strength Indicator sections. Updated the Absolute Maximum Ratings for the FIL+ pin; removed Note 1 and renumbered notes in the DC Electrical Characteristics table and removed the LOP, LOL Voltage Low min specification. Removed the Chip Topography section. DESCRIPTION PAGES CHANGED -- 15 14 1 2 1, 2, 3
MAX3676
1, 8
4
3/09
2, 3 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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